Apple’s patent graphics for creating tamper-resistant code

Posted by Dennis Sellers Nov 3, 2005 at 12:27pm

Part 2: Illustrations contained in patent application 20050246554

System level Overview

FIG. 1 is a block diagram illustrating a system for creating tamper-resistant code using dynamic translation, according to exemplary embodiments of the invention;

FIG. 2 is a block diagram illustrating a system for creating tamper-resistant code using static translation, according to exemplary embodiments of the invention;

Exemplary implementation

FIG. 3 is a flow diagram illustrating operations for creating, translating, and executing software, according to exemplary embodiment of invention;

FIG. 4 is a flow diagram illustrating operations for translating and executing object code, according to exemplary embodiments of the invention;

FIG. 5 is a flow diagram illustrating operations for statically translating and executing an object code program, according to exemplary embodiments of the invention;

FIG. 6 is a flow diagram illustrating operations for servicing system calls based on a tamper-resistance policy, according to exemplary embodiments of the invention;
Methods of the invention
This section describes methods performed by embodiments of the invention. In certain embodiments, the methods are performed by instructions stored on machine-readable media (e.g., software), while in other embodiments, the methods are performed by hardware or other logic (e.g., digital logic).

FIG. 7 is a flow diagram illustrating a method for creating tamper-resistant code using dynamic translation, according to exemplary embodiments of the invention. The flow diagram 700 commences at block 702, wherein a first object code block is received. The flow continues at block 704. At block 704, the first object code block is translated into a second code block. The flow continues at block 706. At block 706, the second code block is executed. From block 706, the flow ends.

FIG. 8 is a flow diagram illustrating operations for creating tamper-resistant code using identifier-based code obfuscation, according to exemplary embodiments of the invention. The flow diagram 800 begins at block 802. At block 802, an identifier is determined based on a machine state. The flow continues at block 804. At block 804, a first object code block is translated into a second object code block and the second object code block is obfuscated using the identifier. The flow continues at block 906. At block 806, the first block is executed. From block 806, the flow ends.

FIG. 9 is a flow diagram illustrating operations for servicing system calls based on a tamper-resistance policy, according to exemplary embodiments of the invention. The flow diagram 900 begins at block 902. At block 902, a first object code block’s system call is received, wherein the system call is formatted for requesting a service from a first operating system. The flow continues at block 904. As shown in block 904, it is determined which system call services of a second operating system are needed for providing the service. The flow continues at block 906. At block 906, it is determined, based on a tamper-resistance policy, whether system call services for servicing the system call have been disabled. The flow continues at block 908. As shown block 908, the system call is serviced if the system calls for servicing the system call have not been disabled. From block 908, the flow ends.

FIG. 10 is a flow diagram illustrating operations for translating and obfuscating object code when it is installed, according to exemplary embodiments of the invention. The flow diagram 1000 begins at block 1002. At block 1002, a first object code program is installed, the first object code program is translated into a second object code program, and the first object code program or the second object code program is obfuscated. The flow continues at block 1004. As shown in block 1004, the second object code program is stored for execution. From block 1004, the flow ends.

This section provides an overview of the exemplary hardware and the operating environment in which embodiments of the invention can be practiced.

FIG. 11 illustrates an exemplary computer system used in conjunction with certain embodiments of the invention. As illustrated in FIG. 11, computer system 1100 comprises processor(s) 1102. The computer system 1100 also includes a memory unit 1130, processor bus 1122, and Input/Output controller (IOC) 1124. The processor(s) 1102, memory unit 1130, and IOC 1124 are coupled to the processor bus 1122. The processor(s) 1102 may comprise any suitable processor architecture. The computer system 1100 may comprise one, two, three, or more processors, any of which may execute a set of instructions in accordance with embodiments of the present invention.

Macsimum Note: For more on “Hardware and Operating Environment,” see patent at patent point 66.

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