Apple patents involve partial, unaligned vectors
Posted by Dennis Sellers 
May 15, 2008 at 10:43am
Apple patents for efficiently accessing unaligned partial vectors and efficiently accessing unaligned vectors have appeared at the U.S. Patent & Trademark Office).
Patent number 20080114969 relates to techniques for improving computer system performance. More specifically, the present invention relates to instructions for efficiently accessing a partial vector located at an arbitrarily aligned memory address.
One embodiment provides a processor that is configured to execute load-swapped-partial instructions. An instruction fetch unit within the processor is configured to fetch the load-swapped-partial instruction to be executed. Note that the load-swapped-partial instruction specifies a source address in a memory, which is possibly an unaligned address.
What’s more, an execution unit within the processor is configured to execute the load-swapped-partial instruction. This involves loading a partial-vector-sized datum from a naturally-aligned memory region encompassing the source address. While loading the partial-vector-sized datum, bytes of the partial-vector-sized datum are rotated to cause the byte at the specified source address to reside at the least-significant byte position within the partial-vector-sized datum for a little-endian memory transaction, or to cause the byte to be positioned at the most-significant byte position within the partial-vector-sized datum for a big-endian memory transaction.
Patent number 20080114969 relates to techniques for improving computer system performance. More specifically, the present invention relates to instructions for efficiently accessing a vector located at an arbitrarily aligned memory address.
According to Apple, one embodiment of the present invention provides a processor which is configured to execute load-swapped instructions, which are possibly directed to unaligned source address. The processor is configured to execute the load-swapped instruction by loading a vector from a naturally-aligned memory region encompassing the source address, and in doing so rotating the bytes of the vector to cause the byte at the specified source address to reside at the least-significant byte position within the vector for a little-endian memory transaction, or causing said byte to be positioned at the most-significant byte position within the vector for a big-endian memory transaction.
In a variation on this embodiment, the processor is also configured to execute a store-swapped instruction directed to a destination address by storing a vector into a naturally-aligned memory region encompassing the destination address, and in doing so rotating the bytes of the vector to cause the least significant byte of the vector to be stored to at the specified destination address on a little-endian processor, or causing the most significant byte of the vector to be stored to the destination address said on a big-endian processor, or causing the specified byte to be stored to the destination address in the case of an endian-specific store-swapped variant.
The inventors listed on both patents are Jeffry E. Gonion and Keith E. Diefendorff.
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Contributor
Dennis Sellers
Dennis has been a newspaper editor/reporter (seven years) and teacher (seven years). He has over 4,000 magazine, newspaper and online articles to his credit. He has also covered the Mac and tech industries for over a decade for such online publications as MacCentral, MacMinute and now MacsimumNews.
